Semiconductor device

ABSTRACT

A semiconductor device ( 1 ) includes an n-type silicon carbide substrate ( 2 ) of a high impurity concentration, an n-type silicon carbide layer ( 3 ) of a low impurity concentration disposed on the substrate, a first n-type silicon carbide region ( 4 ) of a first impurity concentration disposed on the surface of the n-type silicon carbide layer, first p-type silicon carbide regions ( 5 ) disposed as adjoined to the opposite sides of the first n-type silicon carbide region, a second n-type silicon carbide region ( 6 ) disposed selectively from the surface through the interior of the first p-type silicon carbide region, polycrystalline silicon ( 7 ) short-circuiting the first p-type silicon carbide region ( 5 ) to the second n-type silicon carbide region ( 6 ), a gate electrode ( 8 ) and a third n-type silicon carbide region ( 10 ), wherein the components thereof are individually constructed in a vertical DMOS structure. Since the polycrystalline silicon short-circuits the first p-type silicon carbide region to the second n-type silicon carbide region, the threshold voltage can be given a fixed value, and the device can be used as an actual MISFET.

TECHNICAL FIELD

This invention relates to a semiconductor device using silicon carbideas a semiconductor material and including a metal-insulatingfilm-semiconductor field effect transistor (MISFET) called a verticalDMOS structure.

BACKGROUND ART

Since silicon carbide (SiC) has a wide band gap and has a maximumdielectric breakdown field larger by about one order than silicon (Si),this material is expected to be applied to power semiconductor devices.Among other power semiconductor devices, the MISFET of the vertical DMOSstructure is expected to provide extremely low-loss high-speed powerdevices which surpass the performance of the Si power devices becausethe value of the resistance thereof in the on-state (on-resistance) isexpected theoretically to be lower by about two orders than the SiMOSFET.

The MISFET using SiC, however, is known to reveal poor quality of theinterface between the gate insulating film and SiC and extreme smallnessof the channel mobility. For example, J. A. Cooper et al. (Mat. Res.Soc. Proc., Vol. 572, pp. 3-14) have been trying to lower the activatingannealing temperature of a p-type impurity with a view to lowering theon-resistance of the MISFET of the vertical DMOS structure, but havebarely improved the channel mobility to a level of about 20 to 25cm²/Vs. Since the channel resistance is consequently high, their efforthas not yet succeeded in lowering the on-resistance of the MISFET.

As one of the means to efficiently lower the channel resistance, thecurtailment of the channel length proves effective. This means, however,results in suffering the punch through phenomenon to gain inconspicuousness and deteriorating the reverse direction blocking voltageof the MISFET. Precisely, the on-resistance and the reverse directionblocking voltage of the power MISFET are in a trade-off relationship.Thus, the desirability of inventing a device structure which reconcilesthese factors with a favorable characteristic property has been findingrecognition.

The MISFET of a vertical DMOS structure is disclosed in FIG. 2 of M. A.Capano et al. (Journal of Applied Physics, Vol. 87 (2000), pp.8773-8777) and in FIG. 1 of R. Kumar et al. (Japanese Journal of AppliedPhysics, Vol. 39 (2000), pp. 2001-2007). The articles of M. A. Capano etal. and R. Kumar et al. contributed to the literature, have no mentionof any structural device for exaltation of blocking voltage, any buriedchannel structure meeting the need to lower the on-resistance, or anymethod for establishing contact between the P-well and a source region.

The actual MISFET of the vertical DMOS structure using a silicon carbidesubstrate has low channel mobility and incurs difficulty in acquiring anideal blocking voltage as described above. Thus, a device whichpossesses a high blocking voltage property making the most of thephysical properties of SiC and a low on-resistance resistance as wellhas not been realized.

This invention has been initiated in view of the true state of affairsmentioned above and is aimed at providing, in the MISFET of the verticalDMOS structure using a silicon carbide substrate, a semiconductor devicewhich is enabled to acquire an excellent reverse direction blockingvoltage property and lower the on-resistance by optimizing the sourcestructure and the blocking voltage structure and also optimizing thesurface orientation of the silicon carbide substrate.

DISCLOSURE OF THE INVENTION

The semiconductor device contemplated by this invention comprises ann-type silicon carbide substrate of a high impurity concentration, ann-type silicon carbide layer of a low impurity concentration disposed onthe substrate, a first n-type silicon carbide region of a first impurityconcentration disposed on the surface of the n-type silicon carbidelayer, first p-type silicon carbide regions adjoining the opposite sidesof the first n-type silicon carbide region, a second n-type siliconcarbide region of a second impurity concentration disposed selectivelyfrom the surface through the interior of the first p-type siliconcarbide region at a position separated from the first n-type siliconcarbide region, polycrystalline silicon having metal or impurityimplanted therein and serving to short-circuit the first p-type siliconcarbide region to the second n-type silicon carbide region, a gateelectrode disposed in the surface part of the first p-type silicon abideregion through a gate insulating film, and a third n-type siliconcarbide region of a third impurity concentration disposed selectivelyfrom the surface through the interior of the first p-type siliconcarbide region either between the first n-type silicon carbide regionand the first p-type silicon carbide region below the gate electrode orbetween the second n-type silicon carbide region and the first p-typesilicon carbide region below the gate electrode, or both, and has thesecomponents formed in a vertical DMOS structure.

In the semiconductor device of this invention, the first p-type siliconcarbide region has a lower part formed as a second p-type siliconcarbide region of a higher impurity concentration than the first p-typesilicon carbide region.

The first mentioned semiconductor device of this invention furthercomprises an n-type silicon carbide region formed selectively from thesurface through the interior of the first p-type silicon carbide regionbelow the gate electrode, wherein the n-type silicon carbide region hasan impurity concentration enough for serving as a buried channel regionand has a layer thickness which is 0.2 to 1.0 times the layer thicknessof the second n-type silicon carbide region.

In the third mentioned semiconductor device of this invention, theburied channel region has an impurity concentration in the range of5×10¹⁵ to 1×10¹⁷ cm⁻³.

In any one of the first to fourth mentioned semiconductor devices ofthis invention, the gate electrode is formed of aluminum, analuminum-containing alloy or molybdenum.

In any one of the first to fourth mentioned semiconductor devices ofthis invention, the gate electrode is formed of p-type polycrystallinesilicon having boron doped therein at a concentration in the range of1×10¹⁶ to 1×10²¹ cm⁻³.

In any one of the first to fourth mentioned semiconductor devices ofthis invention, the gate electrode is formed of n-type polycrystallinesilicon having phosphorus or arsenic implanted therein at aconcentration in the range of 1×10¹⁶ to 1×10²¹ cm⁻³.

Any one of the first to fourth mentioned semiconductor devices of thisinvention further comprises a silicide film superposed on the gateelectrode, wherein the silicide film is formed of silicon and any one oftungsten, molybdenum and titanium.

In any of the first to fourth mentioned semiconductor devices of thisinvention, the n-type substrate of the high impurity concentration isformed of a hexagonal Or rhombohedral silicon carbide single crystal,and the n-type silicon carbide layer of the low impurity concentrationis formed on a (11-20) face or a (000-1) face of the n-type substrate.

The semiconductor device contemplated by this invention is enabled bybeing constructed as described above to acquire improved channelmobility, retain the threshold voltage at a fixed value, attain an idealblocking voltage and permit provision of a MISFET suitable for practicaluse.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram schematically illustrating a cross section of thesemiconductor device according to the first embodiment of thisinvention.

FIG. 2 is a diagram schematically illustrating a cross section of thesemiconductor device according to the second embodiment of thisinvention.

FIG. 3 is a diagram schematically illustrating a cross section of thesemiconductor device according to the third embodiment of thisinvention.

FIG. 4 is a diagram schematically illustrating a cross section of thesemiconductor device according to the fourth embodiment of thisinvention.

FIG. 5 is a diagram showing the dependency of the channel mobility of asample of Example 4 on Lbc+Xj (Lbc/Xj).

FIG. 6 is a diagram showing the relation between the impurityconcentration and the channel mobility of a buried channel region of thesample of Example 4.

FIG. 7 is a diagram showing the relation between the impurityconcentration and the threshold voltage of a gate electrode of thesample of Example 4.

BEST MODE OF EMBODYING THE INVENTION

FIG. 1 is a diagram schematically illustrating a cross section of thesemiconductor device according to the first embodiment of thisinvention. With reference to FIG. 1, a semiconductor device 1 is ametal-insulating film-semiconductor field effect transistor (MISFET) ofa vertical DMOS structure using a silicon carbide substrate and it iscomposed of an n-type silicon carbide substrate 2 of a high impurityconcentration, an n-type silicon carbide layer 3 of a low impurityconcentration disposed thereon, and the individual components superposedthereon.

Specifically, on the surface of the n-type silicon carbide layer 3, afirst n-type silicon carbide region (N⁻ layer) 4 of a first impurityconcentration is formed at the center and first p-type silicon carbideregions (p-type (P-)wells) 5, 5 are formed as adjoined respectively tothe opposite sides of the first n-type silicon 4.

Then, in the first p-type silicon carbide regions 5, 5, second n-typesilicon carbide regions (N⁺ sources) 6, 6 of a second impurityconcentration are formed selectively from the surface through theinterior of the first p-type silicon carbide regions 5, 5 at positionsseparated from the first n-type silicon carbide region 4. Also, ametallic wiring 7 formed of aluminum, copper or an alloy thereof is laidso as to short-circuit the first p-type silicon carbide regions 5 to thesecond n-type silicon carbide regions 6.

Further, gate electrodes 8, 8 are formed in part of the surfaces of thefirst p-type silicon carbide regions 5, 5 through gate insulating films(gate oxide films) 9, 9. Then, a drain electrode 11 is formed on therear side of the n-type silicon carbide substrate 2.

In the first p-type silicon carbide regions 5, 5 between the secondn-type silicon carbide regions (N⁺ sources) 6, 6 and the first p-typesilicon carbide regions (P-wells) 5, 5 below the gate electrodes 8, 8,third n-type silicon carbide regions (N⁻ regions) 10, 10 are formedselectively from the surface through the interior thereof. Theindividual parts 1 to 10 mentioned above are formed in a vertical DMOSstructure.

In the semiconductor device 1 of the structure mentioned above, when thefirst p-type silicon carbide regions (P-wells) 5 and the second n-typesilicon carbide regions (N⁺ sources) 6 are not short-circuited, thethreshold voltage is not fixed and the MISFET cannot be actually usedbecause the first p-type silicon carbide regions 5 and the second n-typesilicon carbide regions 6 are in an electrically floated state. In thepresent invention, since the first p-type silicon carbide regions(P-wells) 5 and the second n-type silicon carbide regions (N⁺ sources) 6are short-circuited by the use of the metallic wiring 7, the thresholdvoltage is fixed and the MISFET can be actually used. The term“threshold voltage” as used herein refers to a gate voltage which existswhen the MISFET reaches on-state.

Then, in this invention, the third n-type silicon carbide regions (N⁻regions) 10 are formed in the first p-type silicon carbide regions(P-wells) 5 between the second n-type silicon carbide regions (N⁺sources) 6 and the first p-type silicon carbide regions (P-wells) 5below the gate electrodes 8 and the third n-type silicon carbide regions10 are interposed between the gate electrodes 8 and the first p-typesilicon carbide regions 5. Thus, the third n-type silicon carbideregions 10 are enabled to relax the electric field exerted on the gateelectrodes (gate channel regions) 8 and prevent the gate parts fromyielding to the electric field and consequently exalt the blockingvoltage between the drain electrode 11 and the second n-type siliconcarbide regions (N⁺ sources) 6. Further, the hot carrier lifetimeelongated and the effect thereof can be confirmed.

Here, the hot carrier lifetime will be described. The phenomenon inwhich electrons flowing from the source to the drain are injected in ahigh energy state from a semiconductor into an oxide film is called “ahot carrier phenomenon.” When the hot carrier phenomenon occurs, thethreshold voltage is varied because an electric charge is accumulated inthe oxide film. Generally, when the amount of the variation of thethreshold voltage is measured while an operating voltage is beingapplied, the time which elapses till the variation reaches 10% of theinitial value is defined as the hot carrier lifetime. In thisembodiment, since the third n-type silicon carbide regions 10 have a lowimpurity concentration, the electric field is relaxed, and the electronsare not easily allowed to assume a high energy state, the hot carrierphenomenon is suppressed and the hot carrier lifetime is elongated.

FIG. 2 is a diagram schematically illustrating a cross section of thesemiconductor device according to the second embodiment of thisinvention. In FIG. 2, the same component elements as in the firstembodiment will be denoted by the same numerical symbols and they willbe omitted from the following description. A semiconductor device la inthe second embodiment differs from the first embodiment in respect thata third n-type silicon carbide region (N⁻ region) 10 a is intended to beformed in addition to the third n-type silicon carbide region (N⁻region) 10. Specifically, the third n-type silicon carbide region 10 aof a third impurity concentration is formed selectively from the surfacethrough the interior of the first p-type silicon carbide region 5between the first n-type silicon carbide region (N⁻ layer) 4 and thefirst p-type silicon carbide region 5 below the gate electrode 8.

Thus, in the second embodiment, the N⁻ regions 10, 10 a are respectivelyinterposed between the gate electrodes 8 and the first p-type siliconcarbide regions 5 and between the gate electrodes 8 and the first n-typesilicon carbide regions 4. The semiconductor device 1 a, therefore, iscapable of better preventing the gate parts from yielding to an electricfield and is capable of exalting more the blocking voltage between thedrain electrode 11 and the second n-type silicon carbide regions (Ssources) 6 than the semiconductor device 1 of the first embodiment. Ithas been also made possible to uniformize further the resistance of thegate channel region between the two gate electrodes (cells) 8, 8,prevent the occurrence of local current concentration and allay theon-resistance as a whole.

Though the foregoing description has depicted the provision of both thethird n-type silicon carbide regions (N⁻ regions) 10 and 10 a, it ispermissible to use only the third n-type silicon carbide region (N⁻region) 10 a alone in the structure. Even this structure is capable ofmanifesting the effect of exalting the blocking voltage between thedrain electrode 11 and the second n-type silicon carbide region (N⁺source) 6,

FIG. 3 is a diagram schematically illustrating a cross section of thesemiconductor device according to the third embodiment of thisinvention. In FIG. 3, the same component elements as in the first andsecond embodiments will be denoted by the same reference numerals andwill be omitted from the following description. A semiconductor device 1b of this third embodiment differs from the second embodiment in respectthat the lower part of the first p-type silicon carbide region 5 isformed as a second p-type silicon carbide region 5 a of a higherconcentration than the first p-type silicon carbide region 5. Since thethird embodiment forms the lower part of the first p-type siliconcarbide region 5 in a higher impurity concentration as described above,it is enabled to acquire a further improved blocking voltage property.

By shortening the depletion layer from the second p-type silicon carbideregion 5 a, thereby rendering contact with the depletion layer from thesource region 6 difficult, it has been made possible to suppress thepossibility of the application of a high voltage forming a high electricfield between the source region 6 and the n-type silicon carbide layer 3and, as a result, exalting the blocking voltage property.

FIG. 4 is a diagram schematically illustrating a cross section of thesemiconductor device according to the fourth embodiment of thisinvention. In FIG. 4, the same component elements as in the first,second and third embodiments will be denoted by the same referentialnumerals and will be omitted from the following description Asemiconductor device 1 c of this fourth embodiment differs from thethird embodiment in respect that a buried channel region 12 is formed asan n-type silicon carbide region possessing a sufficient impurityconcentration selectively from the surface through the interior of thefirst p-type silicon carbide region 5 below the gate electrode 8. Owingto the provision of the buried channel region 12, the fourth embodimentis enabled to heighten the channel mobility and lower the on-resistancevalue.

Now, the process for the production of the semiconductor device 1 c ofthe fourth embodiment will be roughly described below. In thisinvention, hexagonal silicon carbide or rhombohedral silicon carbide wasadopted for the n-type silicon carbide substrate 2 of the high impurityconcentration and an n-type silicon carbide layer 3 of a low impurityconcentration was formed on the (11-20) face of the hexagonal siliconcarbide or rhombohedral silicon carbide.

Next, on the n-type silicon carbide layer 3, the first n-type siliconcarbide region (N⁻ layer) 4 formed of silicon carbide possessing a firstimpurity concentration was epitaxially grown by the chemical vapordeposition method. Subsequently, the substrate formed of silicon carbideat this stage was given an ordinary RCA cleaning and thereafter analignment mark for lithography was formed thereon by RIE (reactive ionetching).

Then, an LTO (low temperature oxide) film was used as a mask for ionimplantation. This LTO film was formed by reacting silane with oxygen at400° C. to 800° C., thereby depositing silicon dioxide on a siliconcarbide substrate. Next, a region for ion implantation was formed bylithography and the LTO film was etched with HF (hydrofluoric acid) toopen the region for ion implantation. Subsequently, by ion-implantingaluminum or boron into the first n-type silicon carbide region (N⁻layer) 4, the first p-type silicon carbide regions (p-type wells) 5, 5were formed as adjoined to the opposite sides of the first n-typesilicon carbide region (N⁻ layer) 4.

Further, by ion implantation aimed at heightening the blocking voltage,a second p-type silicon carbide region (P⁺ region) 5 a of a higherimpurity concentration than the first p-type silicon carbide region 5was formed in the lower part of the first p-type silicon carbide region5. Then, it was found that the blocking voltage property could beinfallibly improved by having the second p-type silicon carbide regionSa formed by implantation of 10¹⁸ to 10¹⁹ cm⁻³ of aluminum or boron.

Further, the buried channel region 12 was formed as an n-type siliconcarbide region possessing a sufficient impurity concentrationselectively from the surface through the interior of the first p-typesilicon carbide region 5 below the gate electrode 8. This buried channelregion 12 was formed by implanting 1×10¹⁵ to 5×10¹⁷ cm⁻³ of ions at adepth (Lbc) of 0.3 μm.

Next, the second n-type silicon carbide regions (N⁺ sources) 6, 6 of asecond concentration were formed selectively from the surface throughthe interior of the first p-type silicon carbide regions 5, 5 asseparated from the first n-type silicon carbide region 4.

Further, between the second n-type silicon carbide regions (N⁺ sources)6, 6 and the first p-type silicon carbide regions 5, 5 below the gateelectrodes 8, 8 destined to be formed in part of the surfaces of thefirst p-type silicon carbide regions 5, 5 at a subsequent step, thethird n-type silicon carbide regions 10, 10 of a third concentrationwere formed by ion implantation selectively from the surface through theinterior of the first p-type silicon carbide regions 5, 5.

Thereafter, the ensuing composite was subjected to an activating annealin the atmosphere of argon at 1500° C.. Subsequently, it was oxidized at1200° C. to form the gate oxide films 9, 9 about 50 nm in thickness. Itwas then annealed in the atmosphere of argon for 30 minutes and cooledin the atmosphere of argon to room temperature. Thereafter, the gateelectrodes 8, 8 were formed. The gate electrodes 8, 8 were formed of P⁺polysilicon. The formation of the gate electrodes 8, 8 of P⁺ polysiliconmay be accomplished, for example, by 1) a method for accomplishingformation of the p-type polycrystalline silicon by forming apolycrystalline polysilicon by the CVD process and subsequently ionimplantation of boron or boron fluoride into the polycrystallinepolysilicon, 2) a method for attaining formation of the p-typepolycrystalline silicon by forming a polycrystalline polysilicon by theCVD process and subsequently forming a boron-containing SiO₂ film by theCVD process or the spin-coating process and heat-treating the film at800° C. to 1100° C. till diffusion and consequently effectingimplantation of the boron and 3) a method for effecting formation of thep-type polycrystalline silicon by continuing a simultaneous flow ofsilane and diborane and heat-treating this flow at 600° C., therebydoping boron into the polycrystalline silicon. The present embodimentadopted the method of 2). Then, the formation of the gate electrodes 8,8 was completed by etching the resultant composite.

Though the preceding description has presumed to form the gate electrode8 of P⁻ polysilicon, the gate electrode 8 may be formed of N⁺polysilicon, aluminum, an aluminum alloy or molybdenum. It has beenconfirmed that when the gate electrode 8 is formed of aluminum, analuminum alloy or molybdenum, the interface thereof with the gate oxidefilm 9 excels the interface with the gate oxide film 9 using polysiliconfor the gate electrode 8 and brings the effect of exalting the channelmobility.

Either of the gate electrodes 8, 8 had an element possessing a silicidefilm 13 of WSi₂, MoSi₂ or TiSi₂ formed on the N⁺ or P⁺ polysilicon.

Subsequently, interlayer insulating films 14 were deposited by the CVDprocess and the interlayer insulating films 14 on the second n-typesilicon carbide layers (N⁺ sources) 6, 6 and the first p-type siliconcarbide regions (P-wells) 5, 5 were etched to open contact holes. Then,a film of nickel, titanium, aluminum or an alloy thereof was depositedby evaporation or by the spattering process, contacts were formedtherein by RIE or by the wet etching process, and the metallic wiring 7of an alloy containing aluminum or copper was firer formed thereon,thereby short-circuiting the first p-type silicon carbide region 5 tothe second n-type silicon carbide region 6.

In the present embodiment, the metallic wiring 7 was formed byvacuum-depositing aluminum and nickel, forming contacts therein by a wetetching process, then vacuum-depositing aluminum thereon, andwet-etching the resultant component.

Next, on the rear side of the n-type silicon carbide substrate 2, thedrain electrode 11 was formed by attaching a metal thereto by the vacuumdeposition process or the spattering process to a necessary thickness.In the present embodiment, the drain electrode 11 was formed byspattering nickel. Optionally, the resultant composite was heat-treatedin the atmosphere of argon at 1000° C. for five minutes. Thus, an MISfield effect transistor of a vertical DMOS structure was completed.

In the preceding fourth embodiment, the following samples were preparedand tested with the object of clarifying various characteristicproperties.

First, the second p-type silicon carbide region 5 a of a highconcentration formed in the lower part of the first p-type siliconcarbide region 5 by the ion implantation process was examined todetermine the upper limit and the lower limit of impurity concentrationAs a result, it was found that when the impurity concentration of thesecond p-type silicon carbide region (P⁺ region) 5 a was lower than1×10¹⁷ cm⁻³, the voltage causing dielectric breakdown was the same as inthe absence of this P⁺ region, indicating that the region wasineffective, that when the impurity concentration was or exceeded 1×10¹⁷cm⁻³, the voltage causing dielectric breakdown was increased, andtherefore that the lower limit of the impurity concentration was 1×10¹⁷cm⁻³. It was meanwhile found that when the impurity concentrationexceeded 1×10¹⁹ cm⁻³, the impurity was diffused during the course of thesubsequent activating anneal, eventually cancelled the n-type impurityin the overlying buried channel 12 and consequently prevented the buriedchannel 12 from fulfilling the effect thereof and therefore that theupper limit was 1×10¹⁹ cm⁻³.

Next, buried channel regions 12 having depths, Lbe, of 0.1, 0.2, 0.3,0.4, 0.5 and 1.0 μm were formed with the object of investigating therelation between the ratio (Lbc/Xj) of the depth Lbc of the buriedchannel region 12 to the depth Xj of the second n-type silicon carbideregion (N⁺ source) 6 and the channel mobility.

FIG. 5 shows the dependency of the channel mobility on the quotientLbc÷Xj (Lbc/Xj) at the depth Xj of 0.5 μm. In FIG. 5, the channelmobility is standardized with the channel mobility which exists when theburied channel 12 is not provided& That is, the channel mobility is 1 inthe absence of the buried channel region 12. The evaluation was carriedout with the depth Lbc of the buried channel region 12 fixed at 0.1,0.2, 0.3, 0.4, 0.5 and 1.0 μm. The channel mobility was 4.3 when thedepth Lbc was 0.1 μm (Lbc/Xj=0.2) and the channel mobility was 8.4 whenthe depth Lbc was 0.2 μm (Lbc/Xj=0.4), indicating that the buriedchannel region 12 was effective even when the thickness Lbc was 0.1 μm.Meanwhile, the thickness Lbc exceeding 1.0 μm (Lbc/Xj=2) could beactually used only with difficulty because the overage imparted anegative value or normally ON to the threshold in spite of an increasein the channel mobility. Thus, the depth Lbc of the buried channelregion 12 had a lower limit of 0.1 μm and an upper limit of 1.0 μm. Thisrange corresponds to a range of 0.2 to 2.0 in Lbc/Xj. Particularly, therange of 0.2 to 1.0 proves advantageous.

Subsequently, samples having undergone ion implantation to degrees inthe range of 5×10¹⁵ to 5×10¹⁷ cm⁻³ were prepared with the object ofinvestigating the concentration dependency of the buried channel 12relative to the channel mobility.

FIG. 6 is a diagraph showing the relation between the impurityconcentration and the channel mobility in the buried channel region. Thechannel mobility was standardized with the channel mobility whichexisted when the buried channel region 12 was not provided as in thecase of FIG. 5. That is, the channel mobility was 1 when the buriedchannel region 12 was not provided. Since the buried channel region wassatisfactorily effective at the lowest value of impurity concentration,5×10¹⁵ cm⁻³, used for the evaluation, the lower limit of the impurityconcentration was fixed at 5×10¹⁵ cm⁻³. Meanwhile, since the valueexceeding 5×10¹⁷ cm⁻³ produced a negative threshold voltage and renderedactual use of the produced device difficult, the upper limit of thisvalue was fixed at 5×10¹⁷ cm⁻³.

In the present embodiment, the gate electrode 8 made of p-typepolycrystalline silicon (P⁺ polysilicon) was obtained by formingpolycrystalline polysilicon by the CVD process, then forming aboron-containing SiO₂ film by the CVD process or the spin coating andheat-treating the resultant composite at 800° C. to 1100° C., therebydiffusing boron and doping boron as described above. Samples havingimpurity concentration varied from 1×10¹⁵ through 1×10²¹ cm⁻³ wereprepared by performing the heat treatment at 900° C. for varying lengthsof diffusion time with the object of investigating the relation betweenthe impurity concentration and the threshold voltage of the gateelectrode 9 and these samples were tested for threshold voltage.

FIG. 7 is a diagram showing the relation between the impurityconcentration and the threshold voltage of the gate electrode. It isnoted from FIG. 7 that the difference of work function between the gateelectrode and the semiconductor increases and consequently the thresholdincreases in proportion as the impurity concentration in the gateelectrode 8 increases. Conversely, the threshold voltage decreasedproportionately with the decrease of the impurity concentration andreached a zero at an impurity concentration of 1×10¹⁶ cm⁻³. Thus, thelower limit of the impurity concentration was fixed at 1×10¹⁶ cm⁻³.Meanwhile, since the concentration to which boron could be implantedinto the polycrystalline silicon was 1×10²¹ cm⁻³, the upper limit of theimpurity concentration was fixed at 1×10²¹ cm⁻³.

In the fourth embodiment, silicide films 13 of WSi₂, MoSi₂ or TiSi₂ werealso formed on the gate electrodes 8, 8. While the resistance of thegate electrode 8 made of the polycrystalline silicon having boronimplanted to a high concentration therein was several mΩcm, the relativeresistances of the WSi₂, MoSi₂ and TiSi₂ each forming the silicide film13 were respectively 60 μΩcm, 50 μΩcm and 15 μΩcm. The composite film ofpolycrystalline silicon and silicide, therefore, could lower theresistance of the gate electrode than the gate electrode formed solelyof polycrystalline silicon. In the fourth embodiment, the driving forceof the MIS field-effect semiconductor device could be improved.

Further, in the fourth embodiment, the n-type silicon carbide layer 3was formed on the (0001) face, (11-20) face and (000-1) face of thetetragonal or rhombohedral silicon carbide layer having a high impurityconcentration. The DMOS suture MISFET illustrated in FIG. 3 was alsomanufactured on these faces and tested for on-resistance. The blockingvoltage was designed to be 1 kV. The channel mobility of the MISFET was45 cm²/Vs on the (0001) face, 201 cm²/Vs on the (11-20) face and 127cm²/Vs on the (000-1) face. Since the dielectric breakdown field on the(11-20) face was about 70% of that on the (0001) face or the (000-1)face, the value of on-resistance was 33 mΩcm² on the (0001) face, 5mΩcm² on the (11-20) face and 2 mΩcm² on the (000-1) face, that on the(000-1) face being lowest. By using the (11-20) face or the (000-1) facein comparison with the (0001) face which is generally used, therefore,it is made possible to provide DMOS structure MISFETs which possess alow on-resistance.

INDUSTRIAL APPLICABILITY

The semiconductor device contemplated by this invention is enabled byshort-circuiting the first p-type silicon carbide region to the secondn-type silicon carbide region with the polycrystalline silicon having ametal or an impurity implanted therein to impart a fixed value to thethreshold voltage and use the device as an actual MISFET.

Further, since the semiconductor device according to this invention hasthe third n-type silicon carbide region disposed either between thefirst n-type silicon carbide region and the first p-type silicon carbideregion below the gate electrode or between the second n-type siliconcarbide region and the first p-type silicon carbide region below thegate electrode, or both, selectively from the surface through theinterior of the first p-type silicon carbide region, it is capable ofpreventing the gate part of the third n-type silicon carbide region fromyielding to the electric field and consequently exalting the blockingvoltage between the drain electrode and the second n-type siliconcarbide region (N⁺ source) and elongating the lifetime of the hotcarrier as well.

Since the first p-type silicon carbide region has the lower part thereofformed as the second p-type silicon carbide region having a higherconcentration than the first p-type silicon carbide region, it isenabled to exalt the blocking voltage property thereof further.

Further, since the buried channel region is formed selectively from thesurface through the interior of the first p-type silicon carbide regionbelow the gate electrode, the channel mobility can be improved and thevalue of the on-resistance can be lowered.

Since the impurity concentration of the buried channel region is limitedwithin the range of 5×10¹⁵ to 1×10¹⁷ cm⁻³, the channel mobility can beinfallibly improved to several times.

Since the gate electrode is formed of aluminum, an aluminum-containingalloy or molybdenum, the interface thereof with the gate oxide film canbe enhanced and the channel mobility can also be improved.

Further, since the gate electrode is formed of a p-type polycrystallinesilicon having boron implanted therein to a concentration in the rangeof 1×10¹⁶ to 1×10²¹ cm⁻³, the threshold voltage which variesproportionately with the impurity concentration in the gate electrodecan be properly retained.

Since the gate electrode is formed of an n-type polycrystalline siliconhaving phosphorus or arsenic implanted therein to a concentration in therange of 1×10¹⁶ to 1×10²¹ cm⁻³, it is made possible to perform ahigh-temperature heat treatment at not lower than 1,000° C. even afterthe formation of the gate electrode and exalt the characteristicproperties of the MIS field-effect semiconductor device.

Since the silicide film formed of silicon and any one of tungsten,molybdenum and titanium is deposited on the gate electrode, the value ofthe resistance of the gate electro can be lowered below that of the gateelectrode formed solely of polycrystalline silicon, and the drivingforce of the MIS field-effect semiconductor device can be improved.

Further, since the n-type silicon carbide layer of a low impurityconcentration is formed on the (000-1) face and the (11-20) face of then-type substrate of a high impurity concentration which is formed of atetragonal or rhombohedral single crystal, the channel mobility can beimproved and the value of the on-resistance can be lowered.

1. A semiconductor device comprising:. an n-type silicon carbidesubstrate (2) of a high impurity concentration, an n-type siliconcarbide layer (3) of a low impurity concentration disposed on thesubstrate; a first n-type silicon carbide region (4) of a first impurityconcentration disposed on a surface of said n-type silicon carbide layerof the low impurity concentration; first p-type silicon carbide regions(5) disposed as adjoined to opposite sides of said first n-type siliconcarbide region; a second n-type silicon carbide region (6) of a secondimpurity concentration disposed selectively from a surface through aninterior of said first p-type silicon carbide region at a positionseparated from said first n-type silicon carbide region; polycrystallinesilicon (7) having a metal or an impurity implanted therein and servingto short-circuit said first p-type silicon carbide region to said secondn-type silicon carbide region; a gate electrode (8) disposed in asurface part of said first p-type silicon carbide region through a gateinsulating film (9); and a third n-type silicon carbide region (10) of athird impurity concentration formed either between said first n-typesilicon carbide region and the first >type silicon carbide region belowsaid gate electrode or between said second n-type silicon carbide regionand the first p-type silicon carbide region below the gate electrode, orboth, selectively from the surface through the interior of the firstp-type silicon carbide region; all components being individually formedin a vertical DMOS structure.
 2. A semiconductor device according toclaim 1, wherein said first p-type silicon carbide region (5) has alower part formed as a second p-type silicon carbide region (5 a) of ahigher impurity concentration than said first p-type silicon carbideregion.
 3. A semiconductor device according to claim 1, furthercomprising an n-type silicon carbide region (10 a) formed selectivelyfrom the surface through the interior of the first p-type siliconcarbide region below said gate electrode (8), wherein the n-type siliconcarbide region has an impurity concentration sufficient to produce aburied channel region and the buried channel region is formed in a layerthickness 0.2 to 1.0 times a layer thickness of the second n-typesilicon carbide region.
 4. A semiconductor device according to claim 2,further comprising an n-type silicon carbide region (10 a) formedselectively from the surface through the interior of the first p-typesilicon carbide region below said gate electrode (8), wherein the n-typesilicon carbide region has an impurity concentration sufficient toproduce a buried channel region and the buried channel region is formedin a layer thickness 0.2 to 1.0 times a layer thickness of the secondn-type silicon carbide region.
 5. A semiconductor device according toclaim 3 or claim 4, wherein said buried channel region has an impurityconcentration in the range of 5×10¹⁵ to 1×10¹⁷ cm⁻³.
 6. A semiconductordevice according to any one of claims 1 to 4, wherein said gateelectrode (8) is formed of aluminum, an aluminum-containing alloy ormolybdenum.
 7. A semiconductor device according to any one of claims 1to 4, wherein said gate electrode (8) is formed of a p-typepolycrystalline silicon having boron implanted therein to aconcentration in the range of 1×10¹⁶ to 1×10²¹ cm⁻³.
 8. A semiconductordevice according to any one of claims 1 to 4, wherein said gateelectrode (8) is formed of an n-type polycrystalline silicon havingphosphorus or arsenic implanted therein to a concentration in the rangeof 1×10¹⁶ to 1×10²¹ cm³.
 9. A semiconductor device according to any oneof claims 1 to 4, further comprising a silicide film (13) deposited onsaid gate electrode (8), wherein the silicide film is formed of siliconand any one of tungsten, molybdenum and titanium.
 10. A semiconductordevice according to any one of claims 1 to 4, wherein said n-typesilicon carbide layer (3) of a low impurity concentration is formed on a(11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 11. A semiconductor device according to claim 5, whereinsaid n-type silicon carbide layer (3) of a low impurity concentration isformed on a (11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 12. A semiconductor device according to claim 6, whereinsaid n-type silicon carbide layer (3) of a low impurity concentration isformed on a (11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 13. A semiconductor device according to claim 7, whereinsaid n-type silicon carbide layer (3) of a low impurity concentration isformed on a (11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 14. A semiconductor device according to claim 8, whereinsaid n-type silicon carbide layer (3) of a low impurity concentration isformed on a (11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 15. A semiconductor device according to claim 9, whereinsaid n-type silicon carbide layer (3) of a low impurity concentration isformed on a (11-20) face of the n-type substrate (2) of a high impurityconcentration made of a tetragonal or rhombohedral silicon carbidesingle crystal.
 16. A semiconductor device according to any one ofclaims 1 to 4, wherein said n-type silicon carbide layer (3) of a lowimpurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.
 17. A semiconductor deviceaccording to claim 5, wherein said n-type silicon carbide layer (3) of alow impurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.
 18. A semiconductor deviceaccording to claim 6, wherein said n-type silicon carbide layer (3) of alow impurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.
 19. A semiconductor deviceaccording to claim 7, wherein said n-type silicon carbide layer (3) of alow impurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.
 20. A semiconductor deviceaccording to claim 8, wherein said n-type silicon carbide layer (3) of alow impurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.
 21. A semiconductor deviceaccording to claim 9, wherein said n-type silicon carbide layer (3) of alow impurity concentration is formed on a (000-1) face of the n-typesubstrate (2) of a high impurity concentration made of a tetragonal orrhombohedral silicon carbide single crystal.